Semiconductor manufacturing, such as the fabrication of integrated circuits, typically entails the use of photolithography. A semiconductor substrate on which circuits are being formed, usually a silicon wafer, is coated with a material, such as a photoresist, that changes solubility when exposed to radiation. A lithography tool, such as a mask or reticle, positioned between the radiation source and the semiconductor substrate casts a shadow to control which areas of the substrate are exposed to the radiation. After the exposure, the photoresist is removed from either the exposed or the unexposed areas, leaving a patterned layer of photoresist on the wafer that protects parts of the wafer during a subsequent etching or diffusion process.
The photolithography process allows multiple integrated circuit devices or electromechanical devices, often referred to as “chips,” to be formed on each wafer. The wafer is then cut up into individual dies, each including a single integrated circuit device or electromechanical device. Ultimately, these dies are subjected to additional operations and packaged into individual integrated circuit chips or electromechanical devices.
During the manufacturing process, variations in exposure and focus require that the patterns developed by lithographic processes be continually monitored or measured to determine if the dimensions of the patterns are within acceptable ranges. The importance of such monitoring, often referred to as process control, increases considerably as pattern sizes become smaller, especially as minimum feature sizes approach the limits of resolution available by the lithographic process. In order to achieve ever-higher device density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
As a result, careful monitoring of surface features is becoming increasingly important. As design rules shrink, the margin for error in processing becomes smaller. Even small deviations from design dimensions may adversely affect the performance of a finished semiconductor device.
Accordingly, semiconductor customers are requiring high accuracy beam placement to locate features such as single bit fails in memory arrays or locations for circuit edit. Beam shift navigation systems suffer from sample drift, non-linearity in displacement, and are typically limited in field of view. Typical sample stages used on particle beam systems are only accurate to ±1-2 μm. Without a high accuracy stage (like a laser encoded stage) it is not possible to drive the stage directly to the location of interest with accuracy of 100 nm or less. Laser stages may have the capability for 100 nm accuracy but are expensive and limit the system flexibility as the stage generally cannot be tilted, thereby losing functionality. Further, it is desirable to drive sample stages within an accuracy of approximately 30 nm, which is beyond the capability even of typical laser stages.
Thus, there is still a need for an improved method for high accuracy navigation to the site of interest within a local area on a semiconductor surface that will allows beam placement at an accuracy beyond the positional accuracy of the sample stage. Further, there is a need for such an improved method to be suitable for complete or partial automation.